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SI1031-A-GM 数据手册 - Silicon Labs（芯科）
制造商:
Silicon Labs（芯科）
分类:
RF射频器件
封装:
VFLGA-85
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
SI1031-A-GM数据手册
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Rev. 0.3 5
Si102x/3x
11.2.1. DMA0 Memory Access Arbitration........................................................ 149
11.2.2. DMA0 Channel Arbitration .................................................................... 149
11.3. DMA0 Operation in Low Power Modes ......................................................... 149
11.4. Transfer Configuration................................................................................... 150
12. Cyclic Redundancy Check Unit (CRC0)............................................................. 161
12.1. 16-bit CRC Algorithm..................................................................................... 161
12.3. Preparing for a CRC Calculation................................................................... 164
12.4. Performing a CRC Calculation ...................................................................... 164
12.5. Accessing the CRC0 Result.......................................................................... 164
12.6. CRC0 Bit Reverse Feature............................................................................ 168
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)............................... 169
13.1. Polynomial Specification................................................................................ 169
13.2. Endianness.................................................................................................... 170
13.3. CRC Seed Value........................................................................................... 171
13.4. Inverting the Final Value................................................................................ 171
13.5. Flipping the Final Value................................................................................. 171
13.6. Using CRC1 with SFR Access ...................................................................... 172
13.7. Using the CRC1 module with the DMA ......................................................... 172
14. Advanced Encryption Standard (AES) Peripheral............................................ 176
14.1. Hardware Description.................................................................................... 177
14.1.1. AES Encryption/Decryption Core.......................................................... 178
14.1.2. Data SFRs............................................................................................. 178
14.1.3. Configuration sfrs.................................................................................. 179
14.1.4. Input Multiplexer.................................................................................... 179
14.1.5. Output Multiplexer................................................................................. 179
14.1.6. Internal State Machine.......................................................................... 179
14.2. Key Inversion................................................................................................. 180
14.2.1. Key Inversion using DMA...................................................................... 181
14.2.2. Key Inversion using SFRs..................................................................... 182
14.2.3. Extended Key Output Byte Order.......................................................... 183
14.2.4. Using the DMA to unwrap the extended Key........................................ 184
14.3. AES Block Cipher.......................................................................................... 185
14.4. AES Block Cipher Data Flow......................................................................... 186
14.4.1. AES Block Cipher Encryption using DMA............................................. 187
14.4.2. AES Block Cipher Encryption using SFRs............................................ 188
14.5. AES Block Cipher Decryption
........................................................................ 189
14.5.1. AES Block Cipher Decryption using DMA............................................. 189
14.5.2. AES Block Cipher Decryption using SFRs............................................ 190
14.6. Block Cipher Modes ...................................................................................... 191
14.6.1. Cipher Block Chaining Mode................................................................. 191
14.6.2. CBC Encryption Initialization Vector Location....................................... 193
14.6.3. CBC Encryption using DMA.................................................................. 193
14.6.4. CBC Decryption .................................................................................... 196
14.6.5. Counter Mode ....................................................................................... 199
14.6.6. CTR Encryption using DMA.................................................................. 201
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