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SN74LVC1G11DSFR 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
逻辑芯片
封装:
XFDFN-6
描述:
74LVC1G 系列，Texas Instruments低电压 CMOS 逻辑 单门封装 工作电压：1.65 － 5.5 兼容性：输入 LVTTL/TTL、输出 LVCMOS 按 JESD 78 II 级标准，闩锁效应性能超过 100 mA。 ESD 保护超乎 JESD 22 标准 ### 74LVC 系列
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3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P3Hot
典型应用电路图在P1P10P11P12
原理图在P10
封装尺寸在P15P17P18P25
焊盘布局在P26
标记信息在P15P16
封装信息在P14P15P16P17P18
技术参数、封装参数在P4
应用领域在P1P16
电气规格在P5
导航目录
SN74LVC1G11DSFR数据手册
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4
SN74LVC1G11
SCES487H –SEPTEMBER 2003–REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G11
Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
CC
is provided in the Recommended Operating Conditions table.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
V
CC
Supply voltage –0.5 6.5 V
V
I
Input voltage
(2)
–0.5 6.5 V
V
O
Voltage applied to any output in the high-impedance or power-off state
(2)
–0.5 6.5 V
V
O
Voltage applied to any output in the high or low state
(2)(3)
–0.5 V
CC
+ 0.5 V
I
IK
Input clamp current V
I
< 0 –50 mA
I
OK
Output clamp current V
O
< 0 –50 mA
I
O
Continuous output current ±50 mA
Continuous current through V
CC
or GND ±100 mA
T
J
Junction temperature 150 °C
T
stg
Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
1000
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.3 Recommended Operating Conditions
See note
(1)
.
MIN MAX UNIT
V
CC
Supply voltage
Operating 1.65 5.5
V
Data retention only 1.5
V
IH
High-level input voltage
V
CC
= 1.65 V to 1.95 V 0.65 × V
CC
V
V
CC
= 2.3 V to 2.7 V 1.7
V
CC
= 3 V to 3.6 V 2
V
CC
= 4.5 V to 5.5 V 0.7 × V
CC
V
IL
Low-level input voltage
V
CC
= 1.65 V to 1.95 V 0.35 × V
CC
V
V
CC
= 2.3 V to 2.7 V 0.7
V
CC
= 3 V to 3.6 V 0.8
V
CC
= 4.5 V to 5.5 V 0.3 × V
CC
V
I
Input voltage 0 5.5 V
V
O
Output voltage 0 V
CC
V
I
OH
High-level output current
V
CC
= 1.65 V –4
mA
V
CC
= 2.3 V –8
V
CC
= 3 V
–16
–24
V
CC
= 4.5 V –32
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