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SN74LVC1G139DCT 数据手册 - TI（德州仪器）
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SN74LVC1G139DCT数据手册
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V
CC
Unused Input
Input
Output Output
Input
Unused Input
0
1
2
3
4
5
6
7
8
9
0 5 10 15 20 25 30 35 40
ICC (mA)
Frequency (MHz)
VCC=5V
VCC=3.3V
VCC=2.5V
VCC=1.8V
C001
SN74LVC1G139
www.ti.com
SCES602D –AUGUST 2004–REVISED AUGUST 2015
Typical Application (continued)
9.2.3 Application Curve
Figure 5. I
CC
vs Frequency
Load is 15 pF
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions table.
Each V
CC
terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple V
CC
terminals then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or V
CC
, whichever makes more sense or is more convenient.
11.2 Layout Example
Figure 6. Layout Diagram
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