Datasheet 搜索 > 逻辑控制器 > TI（德州仪器） > SN74LVC244ADWRG4 数据手册 > SN74LVC244ADWRG4 数据手册 1/33 页
器件3D模型￥ 1.617
SN74LVC244ADWRG4 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
逻辑控制器
封装:
SOIC-20
描述:
八路缓冲器/驱动器，具有三态输出 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P3P4Hot
典型应用电路图在P1P9P10P11
原理图在P9P10
封装尺寸在P13P14P16P17P25P29
焊盘布局在P26P30
标记信息在P13P14P15
封装信息在P12P13P14P15P16P17
技术参数、封装参数在P4P10
应用领域在P1
电气规格在P6
型号编号列表在P10
导航目录
SN74LVC244ADWRG4数据手册
Page:
of 33 Go
若手册格式错乱，请下载阅览PDF原文件
1
2 18
1Y1
1OE
1A1
4 16
1Y2
1A2
6 14
1Y3
1A3
8 12
1Y4
1A4
19
11 9
2Y1
2OE
2A1
13 7
2Y2
2A2
15 5
2Y3
2A3
17 3
2Y4
2A4
Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC244A
SCAS414AB –NOVEMBER 1992–REVISED NOVEMBER 2016
SN74LVC244A Octal Buffer or Driver With 3-State Outputs
1
1 Features
1
• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Specified From –40°C to +85°C and
–40°C to +125°C
• Maximum t
pd
of 5.9 ns at 3.3 V
• Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25 ° C
• Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25 ° C
• Supports Mixed-Mode Signal Operation on
All Ports (5-V Input or Output Voltage With
3.3-V V
CC
)
• I
off
Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down
to the V
CC
Level
• Available in Ultra Small Logic QFN Package (0.5
mm Maximum Height)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
2 Applications
• Servers
• LED Displays
• Network Switches
• Telecom Infrastructure
• Motor Drivers
• I/O Expanders
3 Description
These octal bus buffers are designed for 1.65-V to
3.6-V VCC operation. The SN74LVC244A devices
are designed for asynchronous communication
between data buses.
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC244AN PDIP (20) 25.40 mm × 6.35 mm
SN74LVC244ANS SO (20) 12.60 mm × 5.30 mm
SN74LVC244ADB SSOP (20) 7.50 mm × 5.30 mm
SN74LVC244ADGV TVSOP (20) 5.00 mm × 4.40 mm
SN74LVC244ADW SOIC (20) 12.80 mm × 7.50 mm
SN74LVC244ARGY VQFN (20) 4.50 mm × 3.50 mm
SN74LVC244AZQN BGA (20) 3.00 mm × 4.00 mm
SN74LVC244APW TSSOP (20) 6.50 mm × 4.40 mm
SN74LVC244ARWP X1QFN (20) 2.50 mm × 3.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
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