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STM32F091CCU6 数据手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
微控制器
封装:
UFQFPN-48
描述:
STMICROELECTRONICS STM32F091CCU6 微控制器, 32位, 线路接入, ARM 皮质-M0, 48 MHz, 256 KB, 32 KB, 48 引脚, UFQFPN
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STM32F091CCU6数据手册
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STM32F091xB/xC silicon limitations STM32F091xB STM32F091xC
4/8 DocID026953 Rev 1
1 STM32F091xB/xC silicon limitations
Table 3 gives quick references to all documented limitations.
Legend for Table 3: A = workaround available; N = no workaround available; P = partial
workaround available, ‘-’ and grayed = fixed.
1.1 System limitations
1.1.1 Wakeup sequence from Standby mode when using more than one
wakeup source
Description
The various wakeup sources are logically OR-ed in front of the rising-edge detector which
generates the wakeup flag (WUF). The WUF needs to be cleared prior to Standby mode
entry, otherwise the MCU wakes up immediately.
If one of the configured wakeup sources is kept high during the clearing of the WUF (by
setting the CWUF bit), it may mask further wakeup events on the input of the edge detector.
As a consequence, the MCU might not be able to wake up from Standby mode.
Workaround
To avoid this problem, the following sequence should be applied before entering
Standby mode:
Disable all used wakeup sources,
Clear all related wakeup flags,
Re-enable all used wakeup sources,
Enter Standby mode
Note: Be aware that, when applying this workaround, if one of the wakeup sources is still kept
high, the MCU will enter Standby mode but then it wakes up immediately generating a
power reset.
Table 3. Summary of STM32F091xB/xC silicon limitations
Section Limitation Rev A
Section 1.1: System limitations
Section 1.1.1: Wakeup sequence from Standby mode
when using more than one wakeup source
A
Section 1.2: USART peripheral limitation
Section 1.2.1: Last byte written in TDR might not be
transmitted if TE is cleared just after writing in TDR
A
Section 1.3: GPIO peripheral limitations
Section 1.3.1: GPIOx locking mechanism not working
properly for GPIOx_OTYPER register
P
Section 1.4: SPI/I2S limitation
Section 1.4.1: In I2S slave mode: WS level must be set
by the external master when enabling the I2S
A
Section 1.5: I2C peripheral limitations
Section 1.5.1: Wrong behaviors in Stop mode when
wakeup from Stop mode is disabled in I2C
A
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