Datasheet 搜索 > 微控制器 > ST Microelectronics（意法半导体） > STM32F091CCU6 数据手册 > STM32F091CCU6 数据手册 6/8 页
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STM32F091CCU6 数据手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
微控制器
封装:
UFQFPN-48
描述:
STMICROELECTRONICS STM32F091CCU6 微控制器, 32位, 线路接入, ARM 皮质-M0, 48 MHz, 256 KB, 32 KB, 48 引脚, UFQFPN
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STM32F091CCU6数据手册
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STM32F091xB/xC silicon limitations STM32F091xB STM32F091xC
6/8 DocID026953 Rev 1
1.5 I
2
C peripheral limitations
1.5.1 Wrong behaviors in Stop mode when wakeup from Stop mode is
disabled in I
2
C
Description
When wakeup from Stop mode is disabled in I
2
C (WUPEN = 0) and the MCU enters Stop
mode while a transfer is on going on the bus, some wrong behaviors may happen:
1. BUSY flag can be wrongly set when the MCU exits Stop mode. This prevents from
initiating a transfer in master mode, as the START condition cannot be sent when
BUSY is set.
2. If clock stretching is enabled (NOSTRETCH = 0), the I
2
C clock SCL may be stretched
low by the I
2
C as long as the MCU is in Stop mode. This limitation may occur when the
Stop mode is entered during the address phase of a transfer on the I
2
C bus while
SCL = 0. Therefore the transfer may be stalled as long as the MCU is in Stop mode.
The probability of the occurrence depends also on the timings configuration, the
peripheral clock frequency and the I
2
C bus frequency.
These behaviors can occur in Slave mode and in Master mode in a multi-master topology.
Workaround
Disable the I
2
C (PE=0) before entering Stop mode and re-enable it in Run mode.
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