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5CSEBA6U23C7N 其他数据使用手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
UBGA-672
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3D模型
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原理图在P12P13P15P22P27P33
技术参数、封装参数在P132
应用领域在P164
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5CSEBA6U23C7N数据手册
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Resetting the Transmitter with the User-Coded Reset Controller During Device Power-
Up ................................................................................................................................................ 3-7
Resetting the Transmitter with the User-Coded Reset Controller During Device
Operation.....................................................................................................................................3-8
Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up
Configuration..............................................................................................................................3-9
Resetting the Receiver with the User-Coded Reset Controller During Device Operation
.....................................................................................................................................................3-10
Transceiver Reset Using Avalon Memory Map Registers....................................................................3-11
Transceiver Reset Control Signals Using Avalon Memory Map Registers............................3-11
Clock Data Recovery in Manual Lock Mode......................................................................................... 3-12
Control Settings for CDR Manual Lock Mode..........................................................................3-13
Resetting the Transceiver in CDR Manual Lock Mode............................................................3-13
Resetting the Transceiver During Dynamic Reconfiguration.............................................................3-14
Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion
Calibration is Required During Device Operation..............................................................3-14
Transceiver Blocks Affected by the Reset and Powerdown Signals....................................................3-15
Transceiver Power-Down.........................................................................................................................3-16
Document Revision History.....................................................................................................................3-16
Transceiver Protocol Configurations in Cyclone V Devices..............................4-1
PCI Express...................................................................................................................................................4-2
PCIe Transceiver Datapath.............................................................................................................4-3
PCIe Supported Features................................................................................................................ 4-4
PCIe Supported Configurations and Placement Guidelines......................................................4-7
Gigabit Ethernet.........................................................................................................................................4-13
Gigabit Ethernet Transceiver Datapath......................................................................................4-15
XAUI............................................................................................................................................................4-19
Transceiver Datapath in a XAUI Configuration.......................................................................4-19
XAUI Supported Features............................................................................................................ 4-21
Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration........... 4-24
Serial Digital Interface...............................................................................................................................4-26
Configurations Supported in SDI Mode.....................................................................................4-27
Serial Digital Interface Transceiver Datapath............................................................................4-29
Serial Data Converter (SDC) JESD204................................................................................................... 4-30
SATA and SAS Protocols..........................................................................................................................4-31
Deterministic Latency Protocols—CPRI and OBSAI...........................................................................4-32
Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode.......4-33
Channel PLL Feedback for Deterministic Relationship...........................................................4-33
CPRI and OBSAI............................................................................................................................4-33
6.144-Gbps Support Capability in Cyclone V GT Devices...................................................... 4-35
CPRI Enhancements......................................................................................................................4-37
Document Revision History.....................................................................................................................4-38
Transceiver Custom Configurations in Cyclone V Devices...............................5-1
Standard PCS Configuration......................................................................................................................5-1
Custom Configuration Channel Options.....................................................................................5-2
Cyclone V Device Handbook Volume 2: Transceivers
TOC-3
Altera Corporation
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