Datasheet 搜索 > DSP数字信号处理器 > NXP（恩智浦） > MSC8156SVT1000B 数据手册 > MSC8156SVT1000B 产品描述及参数 1/69 页
器件3D模型￥ 493.855
MSC8156SVT1000B 产品描述及参数 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
DSP数字信号处理器
封装:
FCBGA-783
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P4P60P61P62P63P64P65Hot
原理图在P3
封装尺寸在P67
型号编码规则在P66
技术参数、封装参数在P24P28P33P34P36P37P38P39P40P41P43P44
电气规格在P24P25P26P27P28P29P30P31P32P33P34P35
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MSC8156SVT1000B数据手册
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FC-PBGA–783
29 mm ⋅ 29 mm
Freescale Semiconductor
Data Sheet
© 2008–2013 Freescale Semiconductor, Inc. All rights reserved.
MSC8156
Document Number: MSC8156
Rev. 6, 7/2013
• Six StarCore SC3850 DSP subsystems, each with an SC3850
DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,
unified 512 Kbyte L2 cache configurable as M2 memory in
64 Kbyte increments, memory management unit (MMU),
extended programmable interrupt controller (EPIC), two
general-purpose 32-bit timers, debug and profiling support,
low-power Wait, Stop, and power-down processing modes, and
ECC/EDC support.
• Chip-level arbitration and switching system (CLASS) that
provides full fabric non-blocking arbitration between the cores
and other initiators and the M2 memory, shared M3 memory,
DDR SRAM controllers, device configuration control and status
registers, MAPLE-B, and other targets.
• 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can
be turned off to save power.
• 96 Kbyte boot ROM.
• Three input clocks (one global and two differential).
• Five PLLs (three global and two Serial RapidIO PLLs).
• Multi-Accelerator Platform Engine for Baseband (MAPLE-B)
with a programmable system interface, Turbo decoding, Viterbi
decoding, and FFT/iFFT and DFT/iDFT processing. MAPLE-B
can be disabled when not required to reduce overall power
consumption.
• Two DDR controllers with up to a 400 MHz clock (800 MHz data
rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to
four banks (two per controller) and support for DDR2 and DDR3.
• DMA controller with 32 unidirectional channels supporting 16
memory-to-memory channels with up to 1024 buffer descriptors
per channel, and programmable priority, buffer, and multiplexing
configuration. It is optimized for DDR SDRAM.
• Up to four independent TDM modules with programmable word
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,
up to 62.5 Mbps data rate for each TDM link, and with glueless
interface to E1 or T1 framers that can interface with
H-MVIP/H.110 devices, TSI, and codecs such as AC-97.
• High-speed serial interface that supports two Serial RapidIO
interfaces, one PCI Express interface, and two SGMII interfaces
(multiplexed). The Serial RapidIO interfaces support 1x/4x
operation up to 3.125 Gbaud with a single messaging unit and two
DMA units. The PCI Express controller supports 32- and 64-bit
addressing, x4, x2, and x1 link.
• QUICC Engine technology subsystem with dual RISC
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction
RAM, supporting two communication controllers for two Gigabit
Ethernet interfaces (RGMII or SGMII), to offload scheduling
tasks from the DSP cores, and an SPI.
• I/O Interrupt Concentrator consolidates all chip maskable
interrupt and non-maskable interrupt sources and routes then to
INT_OUT
, NMI_OUT, and the cores.
• UART that permits full-duplex operation with a bit rate of up to
6.25 Mbps.
• Two general-purpose 32-bit timers for RTOS support per SC3850
core, four timer modules with four 16-bit fully programmable
timers, and eight software watchdog timers (SWT).
• Eight programmable hardware semaphores.
• Up to 32 virtual interrupts and a virtual NMI
asserted by simple
write access.
•I
2
C interface.
• Up to 32 GPIO ports, sixteen of which can be configured as
external interrupts.
• Boot interface options include Ethernet, Serial RapidIO interface,
I
2
C, and SPI.
• Supports standard JTAG interface
• Low power CMOS design, with low-power standby and
power-down modes, and optimized power-management circuitry.
• 45 nm SOI CMOS technology.
Six-Core Digital Signal
Processor
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