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SPC563M64L5COAR
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SPC563M64L5COAR数据手册
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April 2016 DocID14499 Rev 9 1/1122
1
RM0015
Reference manual
SPC563Mxx - 32-bit Power Architecture
®
based MCU with up to
1.5 Mbyte Flash and 111 Kbyte RAM memories
Preface
Overview
The primary objective of this document is to define the functionality of the SPC563Mxx
family of microcontrollers for use by software and hardware developers. The SPC563Mxx
family is built on Power Architecture
®
technology and integrate technologies that are
important for today’s lower-end applications.
As with any technical documentation, it is the reader’s responsibility to be sure he or she is
using the most recent version of the documentation.
To locate any published errata or updates for this document, visit the www.st.com.
Audience
This manual is intended for system software and hardware developers and applications
programmers who want to develop products with the SPC563Mxx device. It is assumed that
the reader understands operating systems, microprocessor system design, basic principles
of software and hardware, and basic details of the Power Architecture.
Chapter Organization and Device-Specific Information
This document includes chapters that describe:
The device as a whole
The functionality of the individual modules on the device
In the latter, any device-specific information is presented in the section “Information Specific
to This Device” at the beginning of the chapter.
References
In addition to this reference manual, the following documents provide additional information
on the operation of the SPC563Mxx:
IEEE-ISTO 5001™ - 2003 and 2010, The Nexus 5001™ Forum Standard for a Global
Embedded Processor Debug Interface
IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan
Architecture
www.st.com

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