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5CSEBA2U23C8SN 产品设计参考手册 - Altera（阿尔特拉）
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Altera（阿尔特拉）
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FPGA芯片
封装:
UBGA-672
描述:
FPGA - 现场可编程门阵列 CycloneV SoC SE SNGL -core ARM Cortex-A9
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Cyclone V GX, GT, and E Device Errata
2015.09.18
ES-1035
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This document lists the errata for the Cyclone
®
V GX, GT, and E devices.
JTAG Programming of 28-nm Devices
JTAG configuration of 28-nm devices does not operate correctly when you initiate a PAUSE_DR instruction
during configuration. In this scenario, JTAG configuration fails when pausing configuration in the middle
of the bit stream by entering into the PAUSE-DR state and continuing to clock the TCK input. The failure
is indicated by CONF_DONE staying low after all of the data has been clocked into the FPGA while nSTATUS
remains high.
The PAUSE-DR feature works correctly with normal IEEE 1149.1 JTAG test operations.
Workaround
If you require pausing in the middle of the bit stream during JTAG configuration, halt the TCK and do
not enter the PAUSE-DR state. Restart the TCK when you resume the configuration.
Status
Affects: Cyclone V GX, GT, and E devices
There is no planned fix for this issue.
External Memory Interface (EMIF) Maximum Frequency Specification
Update
Description
To achieve timing closure, the EMIF maximum frequency specification has been updated in the table
below.
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