Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > 5CSEBA2U23C8SN 数据手册 > 5CSEBA2U23C8SN 产品设计参考手册 2/6 页
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5CSEBA2U23C8SN 产品设计参考手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
UBGA-672
描述:
FPGA - 现场可编程门阵列 CycloneV SoC SE SNGL -core ARM Cortex-A9
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5CSEBA2U23C8SN数据手册
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Table 1: Cyclone V EMIF Maximum Frequency Specification Update
Note: In this table, the stated performances apply to component topology only. The DIMM topology is not
supported on the hard controller.
Note: For changes to other variants and slower speed grades, refer to the External Memory Interface Spec
Estimator.
Device Speed
Grade
Memory
Type
Memory
Topology
Depth
Expansion
Interface
Type
Original
Maximum
Spec (MHz)
Updated
Maximum
Spec (MHz)
Cyclone V
GX/E
-C6 DDR2 Component 2 Chip
Selects
Hard
Controller
400 333
Cyclone V
GX/GT/E
-A7 DDR2 Component 1 Chip Select Hard
Controller
400 333
Cyclone V
GX/GT/E
-A7 DDR2 Component 2 Chip
Selects
Hard
Controller
333 300
Status
Affects: Cyclone V GX, GT, and E devices
Status: No planned fix
Fractional PLL Phase Alignment Error
Description
The fPLL has a silicon sensitivity that causes the static phase error to operate beyond the Quartus
®
II
software expectation. The frequency range and jitter performance of the fPLL meet the Cyclone V Device
Datasheet specifications. This sensitivity is a time zero failure, which means a design affected by this issue
will show failure immediately upon a given device operation over expected operating conditions or will
never show the issue.
The following usage modes may be affected:
• When the fPLL is used for phase compensation. For example, applications that may use phase
compensation include LVDS, board trace matching, or FPGA skew compensation, such as zero delay
buffering.
• Specific IP cores that require fPLL usage.
• Inter-clock domain transfers involving fPLL usage.
Workaround
You can implement design techniques to mitigate inter-clock domain transfers and use the Altera
®
tool to
evaluate fPLL usage and determine if designs may be affected by this issue.
Note:
To determine if your design may be affected, use the Altera fPLL Usage Evaluation Tool.
If you believe your design is affected by this issue, please contact mySupport for further assistance.
2
Fractional PLL Phase Alignment Error
ES-1035
2015.09.18
Altera Corporation
Cyclone V GX, GT, and E Device Errata
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