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LPC11U24FHI33/301, 产品设计参考手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微控制器
封装:
HVQFN-32
描述:
LPC11U2x 系列 6 kB RAM 32 kB 闪存 表面贴装 32位 微控制器 - HVQFN-33
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3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P19P80P128P129P130P131P132P133P134P135P136P137Hot
原理图在P11P12P13P370
型号编码规则在P8P9
功能描述在P58P59P80P167P221P234P260P270P275P282P290P300
应用领域在P168P186P187P188P193P200P202P203P204P215P290P310
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LPC11U24FHI33/301,数据手册
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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 3 of 523
NXP Semiconductors
UM10462
LPC11U3x/2x/1x User manual
5.2 20140331 Modifications:
• Part LPC11U22FBD48/301 added.
• Use of IAP mode with power profiles clarified. Use power profiles in default mode when
executing IAP commands. See Section 20.14 “IAP commands” and Section 5.3.
• Section 5.3 added to clarify use of power profiles.
• Watchdog interrupt flag polarity corrected: This flag is cleared by writing a 1 to the
WDINT bit in the MOD register (Section 17.8.1 “Watchdog mode register”).
• Figure 69 “Boot process flowchart” corrected.
• Table 15 “Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit
description” added.
• Remark added to Section 3.9.4.3 “Wake-up from Deep-sleep mode” and
Section 3.9.5.3 “Wake-up from Power-down mode”: After wake-up, reprogram the clock
source for the main clocks.
• Pin description tables for RESET/PIO0_0 updated: In deep power-down mode, this pin
must be pulled HIGH externally. The RESET pin can be left unconnected or be used as
a GPIO pin if an external RESET function is not needed. See Chapter 8
“LPC11U3x/2x/1x Pin configuration”.
• Pin description notes relating to open-drain I2C-bus pins updated for clarity. Chapter 8
“LPC11U3x/2x/1x Pin configuration”.
• Pin description of the WAKEUP pin updated for clarity. Chapter 8 “LPC11U3x/2x/1x Pin
configuration”.
5.1 20131220 Modifications:
• Reset value of the SYSAHBCLKCTRL register corrected. See Table 5.
• Reserved function added to IOCON pin configuration registers PIO0_8 and PIO0_9.
See Table 69 and Table 70.
• Changed title to “LPC11U3x/2x/1x User manual”.
5 20131120 Modifications:
• Table 121 “GPIO pins available” corrected.
• Table 343 “ISP entry pins for different boot loader versions” added.
• Bit description of the SLEEPDEEP bit corrected in Table 53 “Power control register
(PCON, address 0x4003 8000) bit description”.
• Part LPC11U37HFBD64/401 added.
• API pointer structure updated in Figure 73, Figure 10, and Figure 19.
• Power Profiles API pointer definitions corrected. See Section 5.4.
• Chapter 23 “LPC11U3x/2x/1x I/O Handler” added.
Revision history
…continued
Rev Date Description
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