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5AGXFB3H4F35I3G 数据手册 - Altera（阿尔特拉）
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Altera（阿尔特拉）
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FPGA芯片
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BBGA-1152
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FPGA - 现场可编程门阵列
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5AGXFB3H4F35I3G数据手册
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Symbol Description Maximum Unit
I
XCVR-TX (DC)
DC current per transceiver transmitter (TX) pin 100 mA
I
XCVR-RX (DC)
DC current per transceiver receiver (RX) pin 50 mA
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
Table 1-13: Internal Weak Pull-Up Resistor Values for Arria V Devices
Symbol Description Condition (V)
(11)
Value
(12)
Unit
R
PU
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
V
CCIO
= 3.3 ±5% 25 kΩ
V
CCIO
= 3.0 ±5% 25 kΩ
V
CCIO
= 2.5 ±5% 25 kΩ
V
CCIO
= 1.8 ±5% 25 kΩ
V
CCIO
= 1.5 ±5% 25 kΩ
V
CCIO
= 1.35 ±5% 25 kΩ
V
CCIO
= 1.25 ±5% 25 kΩ
V
CCIO
= 1.2 ±5% 25 kΩ
Related Information
Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
I/O Standard Specifications
Tables in this section list the input voltage (V
IH
and V
IL
), output voltage (V
OH
and V
OL
), and current drive characteristics (I
OH
and I
OL
) for various
I/O standards supported by Arria V devices.
(11)
Pin pull-up resistance values may be lower if an external source drives the pin higher than V
CCIO
.
(12)
Valid with ±10% tolerances to cover changes over PVT.
1-16
Internal Weak Pull-Up Resistor
AV-51002
2016.06.10
Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
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