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AD7302BRU-REEL 数据手册 - ADI（亚德诺）
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AD7302BRU-REEL数据手册
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AD7302
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (B Version) Units Conditions/Comments
t
1
0 ns min Address to Write Setup Time
t
2
0 ns min Address Valid to Write Hold Time
t
3
0 ns min Chip Select to Write Setup Time
t
4
0 ns min Chip Select to Write Hold Time
t
5
20 ns min Write Pulse Width
t
6
15 ns min Data Setup Time
t
7
4.5 ns min Data Hold Time
t
8
20 ns min Write to LDAC Setup Time
t
9
20 ns min LDAC Pulse Width
t
10
20 ns min CLR Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
(V
IL
+ V
IH
)/2. tr and tf should not exceed 1 µs on any digital input.
2
See Figure 1.
A/B
CS
WR
D7–D0
LDAC
CLR
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
t
10
t
9
Figure 1. Timing Diagram for Parallel Data Write
(V
DD
= +2.7 V to +5.5 V; GND = 0 V; Reference = Internal V
DD
/2 Reference;
all specifications T
MIN
to T
MAX
unless otherwise noted)
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