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AD7302BRU-REEL 数据手册 - ADI（亚德诺）
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ADI（亚德诺）
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DA转换器
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AD7302BRU-REEL数据手册
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AD7302
–5–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1-8 D7–D0 Parallel Data Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of CS
and WR.
9 CS Chip Select. Active low logic input.
10 WR Write Input. WR is an active low logic input used in conjunction with CS and A/B to write data to the selected
DAC register.
11 A/B DAC Select. Address pin used to select writing to either DAC A or DAC B.
12 PD Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
13 LDAC Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with
the contents of their DAC registers. If LDAC is permanently tied low, the DACs are updated on the rising
edge of WR.
14 CLR Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all
zeroes and the DAC outputs are cleared to zero volts.
15 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND.
16 REFIN External Reference Input. This can used as the reference for both DACs. The range on this reference input is
1 V to V
DD
/2. If REFIN is directly tied to V
DD
the internal V
DD
/2 reference is selected.
17 AGND Analog Ground reference point and return point for all analog current on the part.
18 V
OUT
B Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output.
19 V
OUT
A Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output.
20 DGND Digital Ground reference point and return point for all digital current on the part.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7302
(MSB) DB7
AGND
V
OUT
B
V
OUT
A
DGND
DB6
DB5
DB4
CLR
V
DD
REFIN
DB3
DB2
DB1
(LSB) DB0
CS
WR
A/B
PD
LDAC
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