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器件3D模型￥ 1.449
AD7948BRSZ 数据手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
DA转换器
封装:
SSOP-20
描述:
ANALOG DEVICES AD7948BRSZ 数模转换器, 12 bit, 17 MSPS, 串行, 3V 至 5.5V, 4.5V 至 5.5V, SSOP, 20 引脚
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AD7948BRSZ数据手册
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AD7943/AD7945/AD7948
REV. B–6–
AD7945 TIMING SPECIFICATIONS
1
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Limit @ Limit @
Parameter V
DD
= +3 V to +3.6 V V
DD
= +4.5 V to +5.5 V Units Description
t
DS
35 20 ns min Data Setup Time
t
DH
10 10 ns min Data Hold Time
t
CS
60 40 ns min Chip Select Setup Time
t
CH
0 0 ns min Chip Select Hold Time
t
WR
60 40 ns min Write Pulsewidth
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DATA VALID
CS
t
CH
t
DS
t
DH
WR
DB11–DB0
t
CS
t
WR
Figure 3. AD7945 Timing Diagram
AD7948 TIMING SPECIFICATIONS
1
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Limit @ Limit @
Parameter V
DD
= +3 V to +3.6 V V
DD
= +4.5 V to +5.5 V Units Description
t
DS
45 30 ns min Data Setup Time
t
DH
10 10 ns min Data Hold Time
t
CWS
0 0 ns min CSMSB or CSLSB to WR Setup Time
t
CWH
0 0 ns min CSMSB or CSLSB to WR Hold Time
t
LWS
0 0 ns min LDAC to WR Setup Time
t
LWH
0 0 ns min LDAC to WR Hold Time
t
WR
60 40 ns min Write Pulsewidth
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DATA
VALID
DATA
VALID
WR
t
CWS
t
CWH
t
CWS
t
CWH
t
LWH
t
LWS
t
DH
t
DS
t
WR
t
WR
t
DH
t
DS
CSMSB
CSLSB
LDAC
DB7–DB0
Figure 4. AD7948 Timing Diagram
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