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CSD95377Q4M 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DC/DC转换器
封装:
VSON-Clip-8
描述:
20V 35A SON 3.5 x 4.5mm 同步降压 NexFET™ 功率级 8-VSON-CLIP -40 to 150
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CSD95377Q4M数据手册
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6
CSD95377Q4M
ZHCSEI7 –DECEMBER 2015
www.ti.com.cn
Copyright © 2015, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The CSD95377Q4M NexFET™ Power Stage is a highly-optimized design for use in a high-power, high-density
synchronous buck converter.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Powering CSD95377Q4M and Gate Drivers
An external V
DD
voltage is required to supply the integrated gate driver IC and provide the necessary gate drive
power for the MOSFETs. TI recommends a 1 µF 10 V X5R or higher ceramic capacitor to bypass V
DD
pin to
P
GND
. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply
to drive the Control FET is generated by connecting a 100 nF 16 V X5R ceramic capacitor between BOOT and
BOOT_R pins. An optional R
BOOT
resistor can be used to slow down the turn-on speed of the Control FET and
reduce voltage spikes on the V
SW
node. A typical 1 Ω to 4.7 Ω value is a compromise between switching loss
and V
SW
spike amplitude.
7.3.2 Undervoltage Lockout (UVLO) Protection
The UVLO comparator evaluates the VDD voltage level. As V
VDD
rises, both the Control FET and Sync FET
gates hold actively low at all times until V
VDD
reaches the higher UVLO threshold (V
UVLO_H
). Then the driver
becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower UVLO threshold
(V
UVLO_L
= V
UVLO_H
– Hysteresis), the device disables the driver and drives the outputs of the Control FET and
Sync FET gates actively low. Figure 1 shows this function.
CAUTION
Do not start the driver in the very-low power mode (SKIP# = Tri-state).
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