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EP1C12F324C7N 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-324
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P162P314P317P377Hot
典型应用电路图在P25P27P29P31P255P273
原理图在P22P141P341
封装尺寸在P12P117P377P383P384
型号编码规则在P11P117
功能描述在P21P148P149P150P152P336P338P340
技术参数、封装参数在P85P86P87P88P89P90P94P113P114P142P224P225
应用领域在P102P203P228
电气规格在P225
导航目录
EP1C12F324C7N数据手册
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Altera Corporation iii
Preliminary
Contents
Chapter Revision Dates ........................................................................... xi
About this Handbook ............................................................................. xiii
How to Find Information ..................................................................................................................... xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiv
Section I. Cyclone FPGA Family Data Sheet
Revision History .................................................................................................................................... 2–1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–1
Document Revision History ................................................................................................................. 1–3
Chapter 2. Cyclone Architecture
Functional Description .......................................................................................................................... 2–1
Logic Array Blocks ................................................................................................................................ 2–3
LAB Interconnects ............................................................................................................................ 2–3
LAB Control Signals ......................................................................................................................... 2–4
Logic Elements ....................................................................................................................................... 2–5
LUT Chain and Register Chain ...................................................................................................... 2–7
addnsub Signal ................................................................................................................................. 2–7
LE Operating Modes ........................................................................................................................ 2–7
MultiTrack Interconnect ..................................................................................................................... 2–12
Embedded Memory ............................................................................................................................. 2–18
Memory Modes ............................................................................................................................... 2–18
Parity Bit Support ........................................................................................................................... 2–20
Shift Register Support .................................................................................................................... 2–20
Memory Configuration Sizes ........................................................................................................ 2–21
Byte Enables .................................................................................................................................... 2–23
Control Signals and M4K Interface .............................................................................................. 2–23
Independent Clock Mode .............................................................................................................. 2–25
Input/Output Clock Mode ........................................................................................................... 2–25
Read/Write Clock Mode ............................................................................................................... 2–28
Single-Port Mode ............................................................................................................................ 2–29
Global Clock Network and Phase-Locked Loops ........................................................................... 2–29
Global Clock Network ................................................................................................................... 2–29
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