Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > EP1C12F324C7N 数据手册 > EP1C12F324C7N 数据手册 4/385 页
器件3D模型￥ 627.157
EP1C12F324C7N 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-324
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P162P314P317P377Hot
典型应用电路图在P25P27P29P31P255P273
原理图在P22P141P341
封装尺寸在P12P117P377P383P384
型号编码规则在P11P117
功能描述在P21P148P149P150P152P336P338P340
技术参数、封装参数在P85P86P87P88P89P90P94P113P114P142P224P225
应用领域在P102P203P228
电气规格在P225
导航目录
EP1C12F324C7N数据手册
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iv Altera Corporation
Preliminary
Cyclone Device Handbook, Volume 1
Dual-Purpose Clock Pins .............................................................................................................. 2–31
Combined Resources ..................................................................................................................... 2–31
PLLs .................................................................................................................................................. 2–32
Clock Multiplication and Division .............................................................................................. 2–35
External Clock Inputs .................................................................................................................... 2–36
External Clock Outputs ................................................................................................................. 2–36
Clock Feedback ............................................................................................................................... 2–37
Phase Shifting ................................................................................................................................. 2–37
Lock Detect Signal .......................................................................................................................... 2–37
Programmable Duty Cycle ........................................................................................................... 2–38
Control Signals ................................................................................................................................ 2–38
I/O Structure ........................................................................................................................................ 2–39
External RAM Interfacing ............................................................................................................. 2–46
DDR SDRAM and FCRAM ........................................................................................................... 2–46
Programmable Drive Strength .....................................................................................................2–49
Open-Drain Output ........................................................................................................................ 2–50
Slew-Rate Control .......................................................................................................................... 2–51
Bus Hold .......................................................................................................................................... 2–51
Programmable Pull-Up Resistor .................................................................................................. 2–51
Advanced I/O Standard Support ................................................................................................ 2–52
LVDS I/O Pins ................................................................................................................................ 2–54
MultiVolt I/O Interface ................................................................................................................. 2–54
Power Sequencing and Hot Socketing ............................................................................................. 2–55
Referenced Documents ....................................................................................................................... 2–56
Document Revision History ............................................................................................................... 2–56
Chapter 3. Configuration and Testing
IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5
Configuration ......................................................................................................................................... 3–5
Operating Modes .............................................................................................................................. 3–6
Configuration Schemes ................................................................................................................... 3–6
Referenced Documents ......................................................................................................................... 3–7
Document Revision History ................................................................................................................. 3–7
Chapter 4. DC and Switching Characteristics
Operating Conditions ........................................................................................................................... 4–1
Power Consumption ............................................................................................................................. 4–8
Timing Model ......................................................................................................................................... 4–9
Preliminary and Final Timing ........................................................................................................ 4–9
Performance .................................................................................................................................... 4–10
Internal Timing Parameters .......................................................................................................... 4–11
External Timing Parameters ......................................................................................................... 4–15
External I/O Delay Parameters .................................................................................................... 4–21
Maximum Input and Output Clock Rates .................................................................................. 4–27
PLL Timing ...................................................................................................................................... 4–29
Referenced Document ......................................................................................................................... 4–31
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