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器件3D模型￥ 627.157
EP1C12F324C7N 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-324
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P162P314P317P377Hot
典型应用电路图在P25P27P29P31P255P273
原理图在P22P141P341
封装尺寸在P12P117P377P383P384
型号编码规则在P11P117
功能描述在P21P148P149P150P152P336P338P340
技术参数、封装参数在P85P86P87P88P89P90P94P113P114P142P224P225
应用领域在P102P203P228
电气规格在P225
导航目录
EP1C12F324C7N数据手册
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Altera Corporation v
Preliminary
Contents
Document Revision History ............................................................................................................... 4–31
Chapter 5. Reference and Ordering Information
Software .................................................................................................................................................. 5–1
Device Pin-Outs ..................................................................................................................................... 5–1
Ordering Information ........................................................................................................................... 5–1
Referenced Documents ......................................................................................................................... 5–2
Document Revision History ................................................................................................................. 5–2
Section II. Clock Management
Revision History .................................................................................................................................... 5–1
Chapter 6. Using PLLs in Cyclone Devices
Introduction ............................................................................................................................................ 6–1
Hardware Overview ........................................................................................................................ 6–1
Software Overview .......................................................................................................................... 6–4
Pins and Clock Network Connections .......................................................................................... 6–6
Hardware Features ................................................................................................................................ 6–8
Clock Multiplication and Division ................................................................................................ 6–8
Phase Shifting ................................................................................................................................... 6–9
Programmable Duty Cycle ........................................................................................................... 6–10
External Clock Output ................................................................................................................... 6–11
Control Signals ................................................................................................................................ 6–12
Clock Feedback Modes ....................................................................................................................... 6–13
Normal Mode .................................................................................................................................. 6–14
Zero Delay Buffer Mode ................................................................................................................ 6–15
No Compensation .......................................................................................................................... 6–15
Pins ......................................................................................................................................................... 6–16
Board Layout ........................................................................................................................................ 6–17
VCCA and GNDA .......................................................................................................................... 6–17
Jitter Considerations ...................................................................................................................... 6–19
Specifications ........................................................................................................................................ 6–20
Software Support ................................................................................................................................. 6–20
Quartus II altpll Megafunction ..................................................................................................... 6–20
altpll Input Ports ............................................................................................................................. 6–22
altpll Output Ports ......................................................................................................................... 6–23
MegaWizard Customization ......................................................................................................... 6–23
MegaWizard Page Description .....................................................................................................6–25
Compilation Report ....................................................................................................................... 6–31
Timing Analysis .............................................................................................................................. 6–33
Simulation ....................................................................................................................................... 6–37
Global Clock Network ........................................................................................................................ 6–38
Dedicated Clock Input Pins .......................................................................................................... 6–40
Dual-Purpose Clock I/O Pins ...................................................................................................... 6–40
Combined Sources .......................................................................................................................... 6–41
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