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1
2
3
6
5
4
BOOST
GND
FB
SW
V
IN
EN
1
2
3
6
5
4
LMR12007
SNVS982 SEPTEMBER 2013
www.ti.com
Connection Diagram
Figure 1. 6-Lead SOT Figure 2. Pin 1 Indentification
See Package Number DDC (R-PDSO-G6)
PIN DESCRIPTIONS
Pin Name Function
1 BOOST Boost voltage that drives the internal NMOS control switch. A bootstrap capacitor is connected between the
BOOST and SW pins.
2 GND Signal and Power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin
for accurate regulation.
3 FB Feedback pin. Connect FB to the external resistor divider to set output voltage.
4 EN Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than V
IN
+ 0.3V.
5 V
IN
Input supply voltage. Connect a bypass capacitor to this pin.
6 SW Output switch. Connects to the inductor, catch diode, and bootstrap capacitor.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
V
IN
-0.5V to 22V
SW Voltage -0.5V to 22V
Boost Voltage -0.5V to 28V
Boost to SW Voltage -0.5V to 6.0V
FB Voltage -0.5V to 3.0V
EN Voltage -0.5V to (V
IN
+ 0.3V)
Junction Temperature 150°C
ESD Susceptibility
(2)
2kV
Storage Temp. Range -65°C to 150°C
Infrared/Convection Reflow (15sec) 220°C
Soldering Information
Wave Soldering Lead Temp. (10sec) 260°C
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) Human body model, 1.5k in series with 100pF.
2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMR12007

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