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SN74LVC125APWRG3
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SN74LVC125APWRG3数据手册
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2A 2Y
2OE
1A 1Y
1OE
4A 4Y
4OE
3A 3Y
3OE
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SN74LVC125A
SCAS290Q JANUARY 1993REVISED JANUARY 2015
SN74LVC125A Quadruple Bus Buffer Gate With 3-State Outputs
1 Features 3 Description
This quadruple bus buffer gate is designed for 1.65-V
1
3-State Outputs
to 3.6-V V
CC
operation.
Separate OE for all 4 buffers
The SN74LVC125A device features independent line
Operates From 1.65 V to 3.6 V
drivers with 3-state outputs. Each output is disabled
Specified From –40°C to 85°C
when the associated output-enable (OE) input is high.
and –40°C to 125°C
To ensure the high-impedance state during power up
Inputs Accept Voltages to 5.5 V
or power down, OE should be tied to V
CC
through a
Max t
pd
of 4.8 ns at 3.3 V
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
Typical V
OLP
(Output Ground Bounce)
driver.
< 0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
Inputs can be driven from either 3.3-V or 5-V devices.
> 2 V at V
CC
= 3.3 V, T
A
= 25°C
This feature allows the use of this device as a
translator in a mixed 3.3-V/5-V system environment.
Latch-Up Performance Exceeds 250 mA
Per JESD 17
Device Information
(1)
ESD Protection Exceeds JESD 22
PART NUMBER PACKAGE (PIN) BODY SIZE
2000-V Human-Body Model
SOIC (14) 8.65 mm × 3.91 mm
200-V Machine Model
SSOP (14) 6.20 mm × 5.30 mm
SN74LVC125A SOP (14) 10.30 mm × 5.30 mm
1000-V Charged-Device Model
TSSOP (14) 5.00 mm × 4.40 mm
VQFN (14) 3.50 mm × 3.50 mm
2 Applications
(1) For all available packages, see the orderable addendum at
Cable Modem Termination Systems
the end of the data sheet.
IP Phones: Wired and Wireless
Optical Modules
4 Simplified Schematic
Optical Networking:
EPON or Video Over Fiber
Point-to-Point Microwave Backhaul
Power: Telecom DC/DC Modules:
Analog or Digital
Private Branch Exchanges (PBX)
TETRA Base Stations
Telecom Base Band Units
Telecom Shelters:
Filter Unit s
Power Distribution Units (PDU)
Power Monitoring Units (PMU)
Wireless Battery Monitoring
Remote Electrical Tilt Units (RET)
Remote Radio Units (RRU)
Tower Mounted Amplifiers (TMA)
Vector Signal Analyzers and Generators
Video Conferencing: IP-Based HD
WiMAX and Wireless Infrastructure Equipment
Wireless Communications Testers
xDSL Modems and DSLAM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC125APWRG3 数据手册

TI(德州仪器)
28 页 / 1.11 MByte

SN74LVC125 数据手册

TI(德州仪器)
具有三态输出的四路总线缓冲器闸
TI(德州仪器)
TEXAS INSTRUMENTS  SN74LVC125APWR  缓冲器/线路驱动器, 非反相, 3态, 4门, 1输入, 1.65V至3.6V, TSSOP-14
TI(德州仪器)
TEXAS INSTRUMENTS  SN74LVC125ADR  缓冲器/线路驱动器, 非反相, 3态, 4门, 1输入, 1.65V至3.6V, SOIC-14
TI(德州仪器)
具有三态输出的增强型产品四路总线缓冲门 14-SOIC -55 to 125
TI(德州仪器)
74LVC 系列反相器和缓冲器,德州仪器德州仪器的 74LVC 系列低功率 CMOS 逻辑集 IC 的一系列反相器和缓冲器。 74LVC 系列使用硅门 CMOS 技术,设计用于在 3.3V 时工作,与 5V 系统相比,允许功耗显著降低。工作电压:1.65 至 3.6V 5V 容差的输入 兼容性:输入 LVTTL/TTL,输出 LVCMOS 按 JESD 17标准,闩锁效应性能超过 250 mA ESD 保护超过 JESD 22 ### 74LVC 系列
TI(德州仪器)
74LVC 系列反相器和缓冲器,德州仪器德州仪器的 74LVC 系列低功率 CMOS 逻辑集 IC 的一系列反相器和缓冲器。 74LVC 系列使用硅门 CMOS 技术,设计用于在 3.3V 时工作,与 5V 系统相比,允许功耗显著降低。工作电压:1.65 至 3.6V 5V 容差的输入 兼容性:输入 LVTTL/TTL,输出 LVCMOS 按 JESD 17标准,闩锁效应性能超过 250 mA ESD 保护超过 JESD 22 ### 74LVC 系列
TI(德州仪器)
74LVC 系列反相器和缓冲器,德州仪器德州仪器的 74LVC 系列低功率 CMOS 逻辑集 IC 的一系列反相器和缓冲器。 74LVC 系列使用硅门 CMOS 技术,设计用于在 3.3V 时工作,与 5V 系统相比,允许功耗显著降低。工作电压:1.65 至 3.6V 5V 容差的输入 兼容性:输入 LVTTL/TTL,输出 LVCMOS 按 JESD 17标准,闩锁效应性能超过 250 mA ESD 保护超过 JESD 22 ### 74LVC 系列
TI(德州仪器)
缓冲器和线路驱动器 Quad Bus Buffer Gate
TI(德州仪器)
四路总线缓冲器闸具有三态输出 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
TI(德州仪器)
TEXAS INSTRUMENTS  SN74LVC125AD.  芯片, 74LVC 逻辑 [ROHS Substitute: 1102975]
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