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STM32L051K8 数据手册 - ST Microelectronics（意法半导体）
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STM32L051K8数据手册
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Contents STM32L051x6/8
2/21 DocID026274 Rev 5
Contents
1 ARM 32-bit Cortex-M0+ limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 STM32L051x6/8 silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Writing in byte mode to the GPIOx_OTYPER register does not work . . . 8
2.1.2 Exiting Stop mode on a reset event is not possible when HSI16 is
the clock system and it is selected as wakeup clock . . . . . . . . . . . . . . . . 8
2.1.3 Protection level1 does not work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4 LSE bypass feature cannot be used in Standby mode . . . . . . . . . . . . . . 9
2.1.5 PA4 and PA5 cannot be redirected to comparator 2 minus input . . . . . . 9
2.1.6 PB14 output speed configuration interferes with PB13 . . . . . . . . . . . . . 10
2.1.7 ADC transfer curve issue at VREF+/2 when VREF+ < VDDA . . . . . . . . 11
2.1.8 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 11
2.1.9 Flash memory wakeup issue when waking up from Stop or Sleep
with Flash in power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.10 Unexpected system reset when waking up from Stop mode with
regulator in low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.11 I2C and USART cannot wake up the device from Stop mode . . . . . . . . 13
2.1.12 LDM, STM, PUSH and POP not allowed in IOPORT bus . . . . . . . . . . . 13
2.1.13 BOOT_MODE bits do not reflect the selected boot mode . . . . . . . . . . . 13
2.2 ADC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Incorrect first ADC conversion result when delay between
two consecutive conversions is too long . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 Overrun flag might not be set when converted data have not been read
before new data are written . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Comparator limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 COMP1_CSR and COMP2_CSR lock bit reset by SYSCFGRST bit
in RCC_APB2RSTR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.2 Output of comparator 2 cannot be internally connected to input 1
of low-power timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 RTC limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 Spurious tamper detection when disabling the tamper channel . . . . . . . 15
2.4.2 Detection of a tamper event occurring before enabling the tamper
detection is not supported in edge detection mode . . . . . . . . . . . . . . . . 15
2.5 I
2
C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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