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STM32L051K8 数据手册 - ST Microelectronics（意法半导体）
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STM32L051K8数据手册
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DocID026274 Rev 5 3/21
STM32L051x6/8 Contents
3
2.5.1 Wrong behaviors in Stop mode when waking up from Stop mode is
disabled in I
2
C peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.2 Wrong data sampling when data set-up time (t
SU;DAT
) is smaller than
one I2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 SPI/I2S peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.1 In I2S slave mode, WS level must to be set by the external master
when enabling the I2S peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.2 BSY bit may stay high at the end of a SPI data transfer in slave mode . 17
2.6.3 Last data bit or CRC calculation may be corrupted for the data received
in master mode depending on the feedback communication
clock timing with respect to the APB clock (SPI or I2S) . . . . . . . . . . . . . 18
2.6.4 CRC may be corrupted when a peripheral connected to the same DMA
channel than the SPI completes its DMA transaction . . . . . . . . . . . . . . 18
2.7 USART limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.1 Start bit detected too soon when sampling for NACK signal
from the smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.2 Break request can prevent the Transmission Complete flag (TC)
from being set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.3 nRTS is active while RE or UE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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