Datasheet 搜索 > 主动器件 > TI（德州仪器） > TSB12LV21APGF 数据手册 > TSB12LV21APGF 数据手册 1/54 页
器件3D模型￥ 84.732
TSB12LV21APGF 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
主动器件
封装:
LQFP
描述:
IEEE1394- 1995总线到PCI总线接口 IEEE 1394-1995 BUS TO PCI BUS INTERFACE
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封装尺寸在P49
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封装信息在P49P50
应用领域在P1P9P50P54
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TSB12LV21APGF数据手册
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若手册格式错乱，请下载阅览PDF原文件
SLLS418I − JUNE 2000 − REVISED DECEMBER 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
D Fully Supports Provisions of IEEE
1394-1995 Standard for High Performance
Serial Bus
†
and the 1394a-2000 Supplement
D Fully Interoperable With FireWire and
i.LINK Implementation of IEEE Std 1394
D Fully Compliant With Open HCI
Requirements
D Provides Three 1394a-2000 Fully Compliant
Cable Ports at 100/200/400 Megabits Per
Second (Mbits/s)
D Full 1394a-2000 Support Includes:
Connection Debounce, Arbitrated Short
Reset, Multispeed Concatenation,
Arbitration Acceleration, Fly-By
Concatenation, Port
Disable/Suspend/Resume
D Extended Resume Signaling for
Compatibility With Legacy DV Devices
D Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power Down During
Suspend, Device Power-Down Terminal,
Link Interface Disable via LPS, and Inactive
Ports Powered Down
D Ultralow-Power Sleep Mode
D Node Power Class Information Signaling
for System Power Management
D Cable Power Presence Monitoring
D Cable Ports Monitor Line Conditions for
Active Connection to Remote Node.
D Register Bits Provide Software Control of
Contender Bit, Power Class Bits, Link
Active Control Bit and 1394a-2000
Features.
D Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
D Interface to Link Layer Controller Supports
Low-Cost TI
Bus-Holder Isolation and
Optional Annex J Electrical Isolation
D Interoperable With Link-Layer Controllers
Using 3.3-V and 5-V Supplies
D Interoperable With Other Physical Layers
(PHYs) Using 3.3-V and 5-V Supplies
D Low-Cost 24.576-MHz Crystal Provides
Transmit Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz.
D Separate Cable Bias (TPBIAS) for Each Port
D Single 3.3-V Supply Operation
D Low-Cost High Performance 80-Pin TQFP
(PFP) Thermally Enhanced Package
D Direct Drop-In Upgrade for
TSB41LV03APFP and TSB41LV03PFP
D Software Device Reset (SWR)
D Fail-Safe Circuitry Senses Sudden Loss of
Power to the Device and Disables the Ports
to Ensure That the TSB41AB3 Does Not
Load the TPBIAS of Any Connected Device
and Blocks Any Leakage From the Port
Back to Power Plane.
D The TSB41AB3 Has a 1394a-Compliant
Common-Mode Noise Filter on the
Incoming Bias Detect Circuit to Filter Out
Crosstalk Noise.
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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†
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation
FireWire is a trademark of Apple Computer, Incorporated.
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