Datasheet 搜索 > 主动器件 > TI（德州仪器） > TSB12LV21APGF 数据手册 > TSB12LV21APGF 数据手册 4/54 页
器件3D模型￥ 84.61
TSB12LV21APGF 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
主动器件
封装:
LQFP
描述:
IEEE1394- 1995总线到PCI总线接口 IEEE 1394-1995 BUS TO PCI BUS INTERFACE
Pictures:
3D模型
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页面导航:
封装尺寸在P49
标记信息在P49
封装信息在P49P50
应用领域在P1P9P50P54
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TSB12LV21APGF数据手册
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of 54 Go
若手册格式错乱，请下载阅览PDF原文件
SLLS418I − JUNE 2000 − REVISED DECEMBER 2004
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
description (continued)
The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise.
When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state
in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put
into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also
held in the disabled state during hardware reset. The TSB41AB3 continues the necessary repeater functions
required for normal network operation regardless of the state of the PHY−LLC interface. When the interface is
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it
to normal operation.
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB3 automatically enters a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB3 disables its internal clock generators and also disables various voltage and current reference
circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when all ports are either disconnected, or disabled with the port’s
interrupt enable bit cleared. The TSB41AB3 exits the low-power mode when the LPS input is asserted high or
when a port event occurs which requires that the TSB41AB3 become active in order to respond to the event
or to notify the LLC of the event (incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port). The SYSCLK output becomes active
(and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high when
the TSB41AB3 is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the
C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which otherwise
causes C/LKON to be active.
The TSB41AB3 is characterized for operation from 0°C to 70°C. The TSB41AB3I is characterized for operation
from −40°C to 85°C.
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