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XCF32PVOG48C 数据手册 - Xilinx（赛灵思）
制造商:
Xilinx（赛灵思）
分类:
EEPROM芯片
封装:
TSOP-48
描述:
XCFxx 配置闪存XCFxx 系列闪存 EPROM 提供易于使用、经济有效和可重新编程方法，用于存储大 Xilinx FPGA 配置比特流。 系统内可编程闪存设备用于配置 Xilinx FPGA IEEE 标准 1149.1/1532 边界扫描 (JTAG) 支持，用于编程、原型设计和测试 级联，用于存储较长或多个比特流 输入/输出引脚，与 +1.5V 至 +3.3V 的电压级别范围兼容 ### Configuration Memory, Xilinx
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XCF32PVOG48C数据手册
Page:
of 35 Go
若手册格式错乱，请下载阅览PDF原文件
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010 www.xilinx.com
Product Specification 27
R
CEO
06 Data Out Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE
input of the next PROM in the chain. This output is
Low when CE
is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value or the PROM does not contain any
blocks that correspond to the selected revision. CEO
returns
to High when OE/RESET
goes Low or CE goes High.
10 D2
05 Output Enable
EN_EXT_SEL
31 Data In
Enable External Selection Input. When this pin is Low, design
revision selection is controlled by the Revision Select pins.
When this pin is High, design revision selection is controlled
by the internal programmable Revision Select control bits.
EN_EXT_SEL
has an internal 50 kΩ resistive pull-up to
V
CCO
to provide a logic 1 to the device if the pin is not driven.
25 H4
REV_SEL0 30 Data In Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low,
the Revision Select pins are used to select the design
revision to be enabled, overriding the internal programmable
Revision Select control bits. The Revision Select[1:0] inputs
have an internal 50 kΩ resistive pull-up to V
CCO
to provide a
logic 1 to the device if the pins are not driven.
26 G3
REV_SEL1 29 Data In 27 G4
BUSY 12 Data In
Busy Input. The BUSY input is enabled when parallel mode
is selected for configuration. When BUSY is High, the internal
address counter stops incrementing and the current data
remains on the data pins. On the first rising edge of CLK after
BUSY transitions from High to Low, the data for the next
address is driven on the data pins. When serial mode or
decompression is enabled during device programming, the
BUSY input is disabled. BUSY has an internal 50 kΩ resistive
pull-down to GND to provide a logic 0 to the device if the pin
is not driven.
5C1
CLKOUT
08 Data Out Configuration Clock Output. An internal Programmable
control bit enables the CLKOUT signal, which is sourced from
either the internal oscillator or the CLK input pin. Each rising
edge of the selected clock source increments the internal
address counter if data is available, CE
is Low, and
OE/RESET
is High. Output data is available on the rising
edge of CLKOUT. CLKOUT is disabled if CE
is High or
OE/RESET
is Low. If decompression is enabled, CLKOUT is
parked High when decompressed data is not ready. When
CLKOUT is disabled, the CLKOUT pin is put into a high-Z
state. If CLKOUT is used, then it must be pulled High
externally using a 4.7 kΩ pull-up to V
CCO
.
9C2
07 Output Enable
TMS – Mode Select
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access Port
(TAP) controller. TMS has an internal 50 kΩ resistive pull-up to
V
CCJ
to provide a logic 1 to the device if the pin is not driven.
21 E2
TCK – Clock
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
20 H3
TDI – Data In
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50 kΩ
resistive pull-up to V
CCJ
to provide a logic 1 to the device if
the pin is not driven.
19 G1
TDO – Data Out
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
50 kΩ resistive pull-up to V
CCJ
to provide a logic 1 to the
system if the pin is not driven.
22 E6
Tabl e 13 : XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Cont’d)
Pin Name
Boundary-
Scan Order
Boundary-
Scan
Function
Pin Description
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
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