Datasheet 搜索 > EEPROM芯片 > Xilinx（赛灵思） > XCF32PVOG48C 数据手册 > XCF32PVOG48C 数据手册 28/35 页
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XCF32PVOG48C 数据手册 - Xilinx（赛灵思）
制造商:
Xilinx（赛灵思）
分类:
EEPROM芯片
封装:
TSOP-48
描述:
XCFxx 配置闪存XCFxx 系列闪存 EPROM 提供易于使用、经济有效和可重新编程方法，用于存储大 Xilinx FPGA 配置比特流。 系统内可编程闪存设备用于配置 Xilinx FPGA IEEE 标准 1149.1/1532 边界扫描 (JTAG) 支持，用于编程、原型设计和测试 级联，用于存储较长或多个比特流 输入/输出引脚，与 +1.5V 至 +3.3V 的电压级别范围兼容 ### Configuration Memory, Xilinx
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标记信息在P30P31P34
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技术参数、封装参数在P13P24P33P35
应用领域在P35
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XCF32PVOG48C数据手册
Page:
of 35 Go
若手册格式错乱，请下载阅览PDF原文件
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010 www.xilinx.com
Product Specification 28
R
XCFxxP VO48/VOG48 Pinout Diagram
VCCINT – – +1.8V Supply. Positive 1.8V supply voltage for internal logic. 4, 15, 34
B1, E1,
G6
VCCO – –
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the output voltage drivers and
input buffers.
8, 30,
38, 45
B2, C6,
D6, G5
VCCJ – –
+3.3V or 2.5V JTAG I/O Supply. Positive 3.3V or 2.5V supply
voltage connected to the TDO output voltage driver and TCK,
TMS, and TDI input buffers.
24 H2
GND – – Ground
2, 7,
17, 23,
31, 36, 46
A1, A2,
B6, F1,
F5, F6, H1
DNC – – Do Not Connect. (These pins must be left unconnected.)
1, 3,
14, 16,
18, 35, 37,
39, 40, 41,
42
A4, C3,
C4, D3,
D4, E3,
E4, F2,
F3, F4,
G2
X-Ref Target - Figure 12
Figure 12: VO48/VOG48 Pinout Diagram (Top View) with Pin Names
Tabl e 13 : XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Cont’d)
Pin Name
Boundary-
Scan Order
Boundary-
Scan
Function
Pin Description
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
DS123_24_031908
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VO48/VOG48
Top
View
DNC
GND
DNC
VCCINT
BUSY
CF
GND
VCCO
CLKOUT
CEO
OE/RESET
CLK
CE
DNC
VCCINT
DNC
GND
DNC
TDI
TCK
TMS
TDO
GND
D7
D6
GND
VCCO
D5
D4
DNC
DNC
DNC
DNC
VCCO
DNC
GND
DNC
VCCINT
D3
D2
GND
VCCO
D1
D0
REV_SEL1
REV_SEL0
EN_EXT_SEL
VCCJ
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