Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > 5CSEBA2U23C8SN 数据手册 > 5CSEBA2U23C8SN 其他数据使用手册 4/169 页
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5CSEBA2U23C8SN 其他数据使用手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
UBGA-672
描述:
FPGA - 现场可编程门阵列 CycloneV SoC SE SNGL -core ARM Cortex-A9
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P12P13P15P22P27P33
技术参数、封装参数在P132
应用领域在P164
导航目录
5CSEBA2U23C8SN数据手册
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若手册格式错乱，请下载阅览PDF原文件
Rate Match FIFO in Custom Configuration................................................................................5-5
Standard PCS in Low Latency Configuration..........................................................................................5-6
Low Latency Custom Configuration Channel Options..............................................................5-7
Document Revision History.....................................................................................................................5-10
Transceiver Loopback Support........................................................................... 6-1
Serial Loopback............................................................................................................................................ 6-1
Forward Parallel Loopback.........................................................................................................................6-2
PIPE Reverse Parallel Loopback................................................................................................................ 6-3
Reverse Serial Loopback..............................................................................................................................6-3
Reverse Serial Pre-CDR Loopback............................................................................................................ 6-4
Document Revision History.......................................................................................................................6-5
Dynamic Reconfiguration in Cyclone V Devices............................................... 7-1
Dynamic Reconfiguration Features...........................................................................................................7-1
Offset Cancellation...................................................................................................................................... 7-2
Transmitter Duty Cycle Distortion Calibration......................................................................................7-3
PMA Analog Controls Reconfiguration...................................................................................................7-3
Dynamic Reconfiguration of Loopback Modes.......................................................................................7-4
Transceiver PLL Reconfiguration .............................................................................................................7-4
Transceiver Channel Reconfiguration......................................................................................................7-5
Transceiver Interface Reconfiguration .................................................................................................... 7-5
Reduced .mif Reconfiguration .................................................................................................................. 7-6
Unsupported Reconfiguration Modes...................................................................................................... 7-6
Document Revision History.......................................................................................................................7-7
TOC-4
Cyclone V Device Handbook Volume 2: Transceivers
Altera Corporation
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