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Altera Corporation Section I–1
Preliminary
Section I. MAX II Device
Family Data Sheet
This section provides designers with the data sheet specifications for
MAX
®
II devices. The chapters contain feature definitions of the internal
architecture, Joint Test Action Group (JTAG) and in-system
programmability (ISP) information, DC operating conditions, AC timing
parameters, and ordering information for MAX II devices.
This section includes the following chapters:
Chapter 1. Introduction
Chapter 2. MAX II Architecture
Chapter 3. JTAG & In-System Programmability
Chapter 4. Hot Socketing & Power-On Reset in MAX II Devices
Chapter 5. DC & Switching Characteristics
Chapter 6. Reference & Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.

EPM240T100I5N 数据手册

Altera(阿尔特拉)
10 页 / 0.13 MByte
Altera(阿尔特拉)
2 页 / 0.09 MByte
Altera(阿尔特拉)
101 页 / 1.01 MByte
Altera(阿尔特拉)
88 页 / 0.8 MByte
Altera(阿尔特拉)
6 页 / 0.08 MByte
Altera(阿尔特拉)
12 页 / 0.26 MByte
Altera(阿尔特拉)
1 页 / 0.14 MByte

EPM240T100I5 数据手册

Altera(阿尔特拉)
CPLD - 复杂可编程逻辑器件 CPLD - MAX II 192 Macro 80 IOs
Intel(英特尔)
Altera(阿尔特拉)
ALTERA  EPM240T100I5N  芯片, CPLD, MAX II, 240单元, TQFP100
Intel(英特尔)
Altera(阿尔特拉)
Intel(英特尔)
Altera(阿尔特拉)
Intel(英特尔)
Intel(英特尔)
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