Datasheet 搜索 > 时钟发生器 > TI（德州仪器） > CDCE72010RGCR 数据手册 > CDCE72010RGCR 产品设计参考手册 1/20 页
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CDCE72010RGCR 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
时钟发生器
封装:
VQFN-64
描述:
十大输出高性能时钟同步器，抖动消除器和时钟经销商 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
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原理图在P13P14P15P16P17P18
功能描述在P2
应用领域在P20
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CDCE72010RGCR数据手册
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若手册格式错乱，请下载阅览PDF原文件
User's Guide
SLAU250 – May 2008
1.5-GHz Low-Phase Noise Clock Evaluation Board
This user's guide discusses the general operation and configuration of the Texas Instruments CDCE72010
evaluation board.
Contents
1 Features ....................................................................................................................... 2
2 General Description ......................................................................................................... 2
3 Signal Path and Control Circuitry ......................................................................................... 3
4 Software Selectable Options .............................................................................................. 3
5 Installing the GUI Interface and USB Driver ............................................................................. 3
6 CDCE72010 Control GUI Interface ....................................................................................... 5
7 TI CDCE72010 Control GUI Interface .................................................................................... 5
7.1 Using Software-Enabled PLL Selection .......................................................................... 5
8 Configuring the Board ..................................................................................................... 10
8.1 Default Configuration for Programming and Testing With USB Cable Attached .......................... 10
8.2 Configuration for Programming With USB Cable Attached .................................................. 10
8.3 Configuration for Testing From a Saved Configuration With USB Cable Removed After
Programming ....................................................................................................... 10
8.4 Configuration for Onboard External Loop Filter ............................................................... 11
8.5 Configuration for PLL Lock Detect .............................................................................. 12
9 CDCE72010EVM Board Schematic Diagram .......................................................................... 13
List of Figures
1 CDCE72010EVM Board .................................................................................................... 2
2 CDCE72010EVM External Loop Filter Topology ....................................................................... 12
Windows is a trademark of Microsoft Corporartion.
SLAU250 – May 2008 1.5-GHz Low-Phase Noise Clock Evaluation Board 1
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