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EP2C8F256C6N 产品设计参考手册 - Intel（英特尔）
制造商:
Intel（英特尔）
封装:
FBGA-256
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P17
功能描述在P38
应用领域在P5P11
导航目录
EP2C8F256C6N数据手册
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Contents
Virtual JTAG Intel
®
FPGA IP Core User Guide......................................................................3
Introduction................................................................................................................ 3
Installing and Licensing Intel FPGA IP Cores........................................................... 4
On-Chip Debugging Tool Suite.............................................................................. 4
Applications of the Virtual JTAG Intel FPGA IP Core..................................................5
JTAG Protocol..................................................................................................... 6
JTAG Circuitry Architecture...................................................................................7
System-Level Debugging Infrastructure.......................................................................... 9
Transaction Model of the SLD Infrastructure............................................................9
SLD Hub Finite State Machine............................................................................. 11
Virtual JTAG Interface Description.................................................................................12
Input Ports.......................................................................................................14
Output Ports.....................................................................................................14
Parameters.......................................................................................................16
Design Flow of the Virtual JTAG Intel FPGA IP Core................................................ 16
Simulation Model.............................................................................................. 17
Run-Time Communication...................................................................................18
Running a DR Shift Operation Through a Virtual JTAG Chain....................................19
Run-Time Communication............................................................................................19
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values................. 20
Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values......................22
Reset Considerations when Using a Custom JTAG Controller.................................... 23
Instantiating the Virtual JTAG Intel FPGA IP Core............................................................24
IP Catalog and Parameter Editor..........................................................................24
Specifying IP Core Parameters and Options...........................................................24
Instantiating Directly in HDL............................................................................... 26
Simulation Support.....................................................................................................28
Compiling the Design..................................................................................................31
Third-Party Synthesis Support.............................................................................32
SLD_NODE Discovery and Enumeration......................................................................... 32
Issuing the HUB_INFO Instruction....................................................................... 33
HUB IP Configuration Register.............................................................................33
SLD_NODE Info Register.................................................................................... 34
Capturing the Virtual IR Instruction Register.................................................................. 35
AHDL Function Prototype ............................................................................................36
VHDL Component Declaration...................................................................................... 36
VHDL LIBRARY-USE Declaration....................................................................................37
Design Example: TAP Controller State Machine...............................................................37
Design Example: Modifying the DCFIFO Contents at Runtime........................................... 39
Write Logic.......................................................................................................39
Read Logic....................................................................................................... 40
Runtime Communication.................................................................................... 41
Design Example: Offloading Hardwired Revision Information............................................ 42
Configuring the JTAG User Code Setting............................................................... 43
Document Revision History for the Virtual JTAG Intel FPGA IP Core User Guide................... 43
Contents
Virtual JTAG Intel
®
FPGA IP Core User Guide
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