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器件3D模型￥ 44.272
ADC124S101CIMMX/NOPB 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
AD转换器
封装:
VSSOP-10
描述:
4 通道、500 ksps 至 1MSPS、12 位模数转换器 10-VSSOP -40 to 85
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P2Hot
典型应用电路图在P18
原理图在P2
封装尺寸在P22P24P25
标记信息在P22
封装信息在P22P23P24P25
焊接温度在P3
技术参数、封装参数在P1P3P5P6P17
应用领域在P1P16
电气规格在P3P4P5P9P10P11P12P13P14P15P19
导航目录
ADC124S101CIMMX/NOPB数据手册
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of 27 Go
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I
OL
200 PA
I
OH
200 PA
1.6V
To Output Pin
C
L
35 pF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8
Track Hold
Power Up
Track Hold
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
9 10
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB11 DB10 DB9 DB8 DB7
DIN
DOUT
Power Up
SCLK
CS
Power Down
Control register
Control register
ADC124S101
SNAS283D –MARCH 2005–REVISED MARCH 2013
www.ti.com
ADC124S101 Timing Specifications (continued)
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 8 MHz to 16 MHz, f
SAMPLE
= 500 ksps to
1 Msps, C
L
= 35 pF, Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(1)
Units
t
CL
SCLK Low Pulse Width 0.5 x t
SCLK
0.3 x t
SCLK
ns (min)
V
A
= +3.0V 1.8
Output Falling
V
A
= +5.0V 1.3
t
DIS
CS Rising Edge to DOUT High-Impedance 20 ns (max)
V
A
= +3.0V 1.0
Output Rising
V
A
= +5.0V 1.0
Timing Diagrams
Figure 3. ADC124S101 Timing Diagram
Figure 4. Timing Test Circuit
6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: ADC124S101
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