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R5F52105BDFM#30 数据手册 - Renesas Electronics(瑞萨电子)
制造商:
Renesas Electronics(瑞萨电子)
分类:
微控制器
封装:
LFQFP-64
描述:
RX210 微控制器RX210 低功率微控制器具有宽工作范围并且可以在高达 50 MHz 78 DMIPS 时执行计算。 使用 RX210 的应用包括数码相机、洗衣机、功率计、智能手机、医疗保健设备和冰箱。工作范围:1.62 V 至 5.3 V 事件链接控制器 (ELC) 多功能引脚控制器 (MPC) 三相电动机控制计时器 (MTU2) 12 位模/数转换器 4 种功耗模式: -睡眠模式 -所有模块时钟停止模式 -软件待机模式 -深度软件待机模式 ### RX 系列微控制器,Renesas ElectronicsRX 系列 32 位闪存微控制器持续发展,用于工业、消费品和办公自动化应用。
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P14P15P16P17P18P19P20P21P22P23P24P25Hot
原理图在P13
封装尺寸在P18P20P23P24P207P208P209P210P211P212P213P214
功能描述在P2P3P4P5P6
技术参数、封装参数在P2P3P4P5P6P87
应用领域在P1
电气规格在P87P88P89P90P91P92P93P94P95P96P97P98
导航目录
R5F52105BDFM#30数据手册
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R01DS0041EJ0150 Rev.1.50 Page 4 of 221
Oct 18, 2013
RX210 Group 1. Overview
Timers 16-bit timer pulse unit
(TPUa)
(16 bits × 6 channels) × 1 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Supports the input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two-phase encoder input) and cascade-
connected operation (32 bits × 2 channels) depending on the channel.
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
(Products with 144 or more pins incorporate a TPU.)
Multi-function timer pulse
unit 2 (MTU2a)
(16 bits 6 channels) 1 unit
Up to 16 pulse-input/output lines and three pulse-input lines are available with six 16-bit timer
channels
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Port output enable 2
(POE2a)
Controls the high-impedance state of the MTU’s waveform output pins
8-bit timer (TMR)
(8 bits 2 channels) 2 units
Select from among seven internal clock signals (PCLK1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,
PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Compare match timer
(CMT)
(16 bits 2 channels) 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Watchdog timer (WDTA)
14 bits 1 channel
Select from among six counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512,
PCLK/2048, PCLK/8192)
Independent watchdog
timer (IWDTa)
14 bits 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Frequ
ency di
vided by 1, 16, 32, 64, 128, or 256
Realtime clock (RTCb)
Clock source: Sub-clock
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Time-capture facility for three values
Table 1.1 Outline of Specifications (3 / 5)
Classification Module/Function Description
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