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AD5331BRU-REEL7 数据手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
DA转换器
封装:
TSSOP
描述:
2.5 V至5.5 V ， 115 μA ，并行接口单电压输出8位/ 10位/ 12位DAC 2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
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原理图在P1P7P8P9P10
封装尺寸在P24
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焊接温度在P6
功能描述在P1P7P8P9P10
技术参数、封装参数在P1P3P6
应用领域在P1P21
电气规格在P13
导航目录
AD5331BRU-REEL7数据手册
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of 28 Go
若手册格式错乱，请下载阅览PDF原文件
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 5 of 28
TIMING CHARACTERISTICS
1, 2, 3
V
DD
= 2.5 V to 5.5 V, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Limit at T
MIN
, T
MAX
Unit Condition/Comments
t
1
0 ns min
CS
to WR setup time.
t
2
0 ns min
CS
to WR hold time.
t
3
20 ns min
WR
pulse width.
t
4
5 ns min Data, GAIN, BUF, HBEN setup time.
t
5
4.5 ns min Data, GAIN, BUF, HBEN hold time.
t
6
5 ns min
Synchronous mode; WR
falling to LDAC falling.
t
7
5 ns min
Synchronous mode; LDAC
falling to WR rising.
t
8
4.5 ns min
Synchronous mode; WR
rising to LDAC rising.
t
9
5 ns min
Asynchronous mode; LDAC
rising to WR rising.
t
10
4.5 ns min
Asynchronous mode; WR
rising to LDAC falling.
t
11
20 ns min
LDAC
pulse width.
t
12
20 ns min
CLR
pulse width.
t
13
50 ns min
Time between WR
cycles.
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 2.
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC
1
LDAC
2
CLR
NOTES:
1
SYNCHRONOUS LDAC UPDATE MODE
2
ASYNCHRONOUS LDAC UPDATE MODE
t
1
t
2
t
3
t
4
t
6
t
7
t
9
t
10
t
11
t
12
t
8
t
5
t
13
06852-002
Figure 2. Parallel Interface Timing Diagram
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