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Figure 56: CAS WRITE Latency
CK
CK#
Command
DQ
DQS, DQS#
ACTIVE n
T0 T1
Don’t Care
NOP NOP
T6 T12
NOPWRITE n
T13
NOP
DI
n + 3
DI
n + 2
DI
n + 1
T14
NOP
DI
n
t
RCD (MIN)
NOP
AL = 5
T11
Indicates break
in time scale
WL = AL + CWL = 11
Transitioning Data
T2
CWL = 6
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-
sure the DRAM never exceeds a case temperature ( T
C
) of 85°C while in self refresh, un-
less the user enables the SRT function when T
C
is between 85°C and 95°C.
Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1x to
2x when T
C
exceeds 85°C. This enables the user to operate the DRAM beyond the stand-
ard 85°C limit up to the optional extended temperature range of 95°C while in self re-
fresh mode.
The standard self refresh current test specifies test conditions for normal T
C
(85°C) only,
meaning that if ASR is enabled, the standard self refresh current specifications do not
apply (see Extended Temperature Usage (page 183)).
SELF REFRESH TEMPERATURE (SRT)
Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1x refresh rate). In the disabled mode, SRT requires the user to en-
sure the DRAM never exceeds a T
C
of 85°C while in self refresh mode, unless the user
enables ASR.
When SRT is enabled, the DRAM self refresh is changed internally from 1x to 2x, regard-
less of T
C
. This enables the user to operate the DRAM beyond the standard 85°C limit up
to the optional extended temperature range of 95°C while in self refresh mode. The
standard self refresh current test specifies test conditions for normal T
C
(85°C) only,
meaning that if SRT is enabled, the standard self refresh current specifications do not
apply (see Extended Temperature Usage (page 183)).
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 2 (MR2)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
147
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.

MT41J128M16JT-093G:K 数据手册

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MT41J128M16JT093 数据手册

Micron(镁光)
同步动态随机存取内存(SDRAM) MT41J128M16JT-093:K FBGA-96
Micron(镁光)
同步动态随机存取内存(SDRAM) MT41J128M16JT-093G:K FBGA-96
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