Datasheet 搜索 > 存储芯片 > Micron（镁光） > MT41J128M16JT-093G:K 数据手册 > MT41J128M16JT-093G:K 数据手册 148/215 页
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MT41J128M16JT-093G:K 数据手册 - Micron（镁光）
制造商:
Micron（镁光）
分类:
存储芯片
封装:
FBGA-96
描述:
同步动态随机存取内存(SDRAM) MT41J128M16JT-093G:K FBGA-96
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P14P15P150
封装尺寸在P22P23P24P25
标记信息在P1P2
功能描述在P12P13P150P196
技术参数、封装参数在P26P27P31P32P33P34P35P36P37P38P39P40
电气规格在P26P27P31P32P33P34P35P36P37P38P39P40
型号编号列表在P2
导航目录
MT41J128M16JT-093G:K数据手册
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SRT versus ASR
If the normal T
C
limit of 85°C is not exceeded, then neither SRT nor ASR is required, and
both can be disabled throughout operation. However, if the extended temperature op-
tion of 95°C is needed, the user is required to provide a 2x refresh rate during manual
refresh and to enable either the SRT or the ASR to ensure self refresh is performed at the
2x rate.
SRT forces the DRAM to switch the internal self refresh rate from 1x to 2x. Self refresh is
performed at the 2x refresh rate regardless of the case temperature.
ASR automatically switches the DRAM’s internal self refresh rate from 1x to 2x. Howev-
er, while in self refresh mode, ASR enables the refresh rate to automatically adjust be-
tween 1x and 2x over the supported temperature range. One other disadvantage of ASR
is the DRAM cannot always switch from a 1x to 2x refresh rate at an exact T
C
of 85°C.
Although the DRAM will support data integrity when it switches from a 1x to 2x refresh
rate, it may switch at a temperature lower than 85°C.
Since only one mode is necessary, SRT and ASR cannot be enabled at the same time.
Dynamic On-Die Termination (ODT)
The dynamic ODT (R
TT(WR)
) feature is defined by MR2[10, 9]. Dynamic ODT is enabled
when a value is selected for the dynamic ODT resistance R
TT(WR)
. This new DDR3
SDRAM feature enables the ODT termination resistance value to change without issu-
ing an MRS command, essentially changing the ODT termination on-the-fly.
With dynamic ODT (R
TT(WR)
) enabled, the DRAM switches from nominal ODT (R
TT,nom
)
to dynamic ODT (R
TT(WR)
) when beginning a WRITE burst, and subsequently switches
back to normal ODT (R
TT,nom
) at the completion of the WRITE burst. If R
TT,nom
is disa-
bled, the R
TT,nom
value will be High-Z. Special timing parameters must be adhered to
when dynamic ODT (R
TT(WR)
) is enabled: ODTLcnw, ODTLcwn4, ODTLcwn8, ODTH4,
ODTH8, and
t
ADC.
Dynamic ODT is only applicable during WRITE cycles. If normal ODT (R
TT,nom
) is disa-
bled, dynamic ODT (R
TT(WR)
) is still permitted. R
TT,nom
and R
TT(WR)
can be used inde-
pendent of one another. Dynamic ODT is not available during write leveling mode, re-
gardless of the state of ODT (R
TT,nom
). For details on dynamic ODT operation, refer to
On-Die Termination (ODT) (page 194).
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 2 (MR2)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
148
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
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