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Figure 58: MPR Block Diagram
Memory core
MR3[2] = 0 (MPR off)
DQ, DM, DQS, DQS#
Multipurpose register
predefined data for READs
MR3[2] = 1 (MPR on)
Notes:
1. A predefined data pattern can be read out of the MPR with an external READ com-
mand.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When
the data flow is defined, the MPR contents can be read out continuously with a regular
READ or RDAP command.
Table 77: MPR Functional Description of MR3 Bits
MR3[2] MR3[1:0]
FunctionMPR MPR READ Function
0 “Don’t Care” Normal operation, no MPR transaction
All subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
1 A[1:0]
(see Table 78 (page 151))
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and
2
MPR Functional Description
The JEDEC MPR definition enables either a prime DQ (DQ0 on x4 and x8; on x16, DQ0 =
lower byte and DQ8 = upper byte) to output the MPR data with the remaining DQ driv-
en LOW, or all DQ to output the MPR data. The MPR readout supports fixed READ burst
and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC
timings applicable, provided the DLL is locked as required.
MPR addressing for a valid MPR read is as follows:
A[1:0] must be set to 00 as the burst order is fixed per nibble.
A2 selects the burst order: BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4,
5, 6, 7.
For burst chop 4 cases, the burst order is switched on the nibble base along with the
following:
A2 = 0; burst order = 0, 1, 2, 3
A2 = 1; burst order = 4, 5, 6, 7
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 3 (MR3)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
150
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.

MT41J128M16JT-093G:K 数据手册

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MT41J128M16JT093 数据手册

Micron(镁光)
同步动态随机存取内存(SDRAM) MT41J128M16JT-093:K FBGA-96
Micron(镁光)
同步动态随机存取内存(SDRAM) MT41J128M16JT-093G:K FBGA-96
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