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EPM240T100I5N 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
CPLD芯片
封装:
TQFP-100
描述:
ALTERA EPM240T100I5N 芯片, CPLD, MAX II, 240单元, TQFP100
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EPM240T100I5N数据手册
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Altera Corporation 5
Preliminary
EPM1270 ES Device Issues
■ UFM block optional oscillator output port can exhibit a single high
or low pulse after power-up
■ Optional Schmitt trigger inputs may glitch for falling input signal
edge rates greater than 1 µs
■ 144-Pin TQFP package (T144) devices may exhibit glitches on the
TCK JTAG input pin for falling edge rates slower than 50 ns
■ May not operate for V
CCINT
brown-out conditions at or below 2.1 V
■ Do not support SVF format programming
■ Are not compatible with the EPM1270 production device POF
1 All of the device issues listed above are corrected in production
EPM1270 devices.
UFM Block Logic Array Interface Support
The EPM1270 ES UFM block does not support write/program and erase
operations from the logic array interface. The EPM1270 ES UFM block
does support read operations from the logic array interface. The UFM can
still be initialized or programmed through the JTAG interface using the
Quartus II software with POF, Jam™ (.jam), or Jam Byte-Code (.jbc) files.
When using the altufm megafunction to instantiate the UFM block, the
Quartus II software issues an error for the following cases:
■ For the interface protocol, choosing None in the MegaWizard
®
Plug-
In Manager
(called the altufm_none megafunction) and
connecting the program or erase ports of your instantiation to signals
or pins in your design results in a compilation error.
■ If you choose Parallel or Serial Peripheral Interface (SPI) in the
MegaWizard
®
Plug-In Manager (called the altufm_parallel and
altufm_spi megafunctions), the read/write option results in a
compilation error. The read-only option will compile successfully.
1 Production devices will fully support the UFM erase and
program/write operations from the logic array.
UFM Block Oscillator Output Port Pulse
The EPM1270 ES device's optional UFM oscillator (OSC) output port, may
pulse once (high or low) at power-up when first entering into user mode
even though the oscillator enable port (OSCENA) is de-asserted at power-
up in the design. The OSC output can be ANDed with the OSCENA port in
the design to ensure that this port starts clocking when expected after
power-up.
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